1. Field of the Invention
The present invention relates to an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a method of driving the same. In particular, the present invention relates to an EEPROM embedded in a liquid crystal driver IC and a method of driving the same.
2. Description of the Related Art
An EEPROM has been often used as an external part of an integrated circuit (IC). In recent years, there is growing demand to embed the EEPROM in an IC itself for the purpose of reducing the number of parts at the time of implementation and adjusting characteristics of a liquid crystal driver IC.
From the aspect of intended purpose, an EEPROM embedded in the liquid crystal driver IC is characterized by the following points: (1) the number of bits can be as small as several bits to several hundreds bits; (2) a few rewritable times are sufficient; (3) the reliability of data holding must be ensured over a long period of time; and (4) increase in the cost must be avoided. Against such a background, an EEPROM having a single-layer poly structure may be used as the embedded EEPROM. Although there is disadvantage in area, the EEPROM with a single-layer poly structure can be fabricated by adding a few processes to the existing CMOS process, which is advantageous in terms of cost.
For example, Japanese Patent Publication No. JP-2596695 discloses a conventional EEPROM having a single-layer poly structure as shown in FIG. 1. The EEPROM (one memory cell) shown in FIG. 1 has an Nch MOS transistor and a Pch MOS transistor. A gate poly 18 of the Nch MOS transistor and the Pch MOS transistor is common. The Nch MOS transistor consists of diffusion layers 12a, 12b and a gate electrode 13. The Pch MOS transistor consists of diffusion layers 15a, 15b, 16 and a gate electrode 17. An N-type well 14 is formed in a P-type semiconductor substrate 20. Terminals 10, 11 and 19 are used for applying voltages to the diffusion layers. Respective of the two MOS transistors are used as a data read transistor and a control gate well capacitor. A gate capacitance of the control gate well capacitor is designed to be smaller than a gate capacitance of the data read transistor. In FIG. 1, the Nch MOS transistor is formed as the data read transistor, while the Pch MOS transistor is formed as the control gate well capacitor.
Operation conditions of the above-described conventional EEPROM are as follows. At the time of data programming, the data is programmed through an FN tunnel current method or a hot carrier injection method in the side of the Nch MOS transistor. At the time of data erasing, the data is erased through the FN tunnel current method in the side of the Nch MOS transistor or the Pch MOS transistor. A data reading is carried out in the side of the Nch MOS transistor. At the time of the data reading, a voltage +Vr is applied to the Pch MOS transistor such that a gate voltage of the memory cell is increased and thereby the data is sensed.